Through carefully orchestrated hierarchical clock gating, near perfect power scaling is achieved. One of the challenges with multi-threading is to have the power scale with the number of threads running. Keeping the speed targets low allows the implementation to avoid many of the power-costly design methods that are typical of high speed design.

Rather than pushing performance through MHz, the designs strive for high levels of work per cycle, but at a reduced clock speed. Energy efficiency is often the more critical metric. Hexagon cores are optimized for both high performance and energy efficiency. At Uplinq 2013, we released the first publicly available development environment for the Hexagon DSP, the Hexagon SDK. The “Hexagon DSP” core is now in its 5th generation and is integrated inside all recent Qualcomm Technologies modem and application chips. As of 2012, multiple Hexagon cores form the processing engine behind virtually every commercially shipping 4G LTE modem by Qualcomm Technologies. In 2011 the Hexagon Access program was started to allow customers to program the DSP and thus exploit the power & performance benefits of offloading the ARM cores for performance, reduced power dissipation, or concurrency requirements.

Qualcomm Technologies began development of a new DSP processor architecture and high-performance implementation in the Fall of 2004.

Digital signal processing audio